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Genesis Microchip Publication
PRELIMINARY DATA SHEET GMZAN3
XGA Analog Interface LCD Monitor Controller
GENESIS MICROCHIP CONFIDENTIAL
Publication Number: C0523-DAT-01G Publication Date: July 2003
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Genesis Microchip Inc.
The following are trademarks or registered trademarks of Genesis Microchip, Inc.:
Genesis , Genesis Display Perfection , ESM , RealColor , Ultra-Reliable DVI , Real Recovery , Sage , JagASM , SureSync , Adaptive Backlight ControlTM, Faroudja , DCDi , TrueLife , IntelliComb
TM TM TM TM TM TM TM TM TM TM TM TM TM
Other brand or product names are trademarks of their respective holders.
(c) Copyright 2003 Genesis Microchip Inc. All Rights Reserved.
Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. It is the customer's responsibility to obtain the most recent revision of the document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this document.
GMZAN3 Preliminary Data Sheet
Table Of Contents
1 Overview ........................................................................................................................................8 1.1 1.2 2 3 4 GMZAN3 System Design Examples ......................................................................................8 GMZAN3 Features .................................................................................................................9
GMZAN3 Pinout ...........................................................................................................................10 GMZAN3 Pin List .........................................................................................................................12 Functional Description .................................................................................................................19 4.1 4.1.1 4.1.2 4.1.3 4.2 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 4.3.7 4.4 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 4.5.6 4.5.7 4.5.8 4.6 4.6.1 4.6.2 4.7 4.8 4.8.1 Clock Generation.................................................................................................................19 Using the Internal Oscillator with External Crystal ........................................................19 Using an External Clock Oscillator.................................................................................22 Clock Synthesis ...............................................................................................................23 Hardware Reset ...................................................................................................................24 Analog to Digital Converter ................................................................................................26 ADC Pin Connection.......................................................................................................26 ADC Characteristics........................................................................................................28 Clock Recovery Circuit...................................................................................................28 Sampling Phase Adjustment............................................................................................29 Integrated Schmitt Trigger for Horizontal and Vertical Sync input................................29 SOG and CSYNC support...............................................................................................30 ADC Capture Window ....................................................................................................31 Test Pattern Generator (TPG)..............................................................................................32 Input Format Measurement .................................................................................................33 Horizontal and Vertical Measurement ............................................................................33 Format Change Detection................................................................................................33 Watchdog ........................................................................................................................34 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only) ......................34 Input Pixel Measurement ................................................................................................34 Image Phase Measurement..............................................................................................34 Image Boundary Detection..............................................................................................34 Image Auto Balance ........................................................................................................34 High-Quality Scaling...........................................................................................................35 Variable Zoom Scaling....................................................................................................35 Horizontal & Vertical Shrink ..........................................................................................35 Gamma LUT........................................................................................................................35 Display Output Interface .....................................................................................................35 Display Synchronization .................................................................................................35
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4.8.2 4.8.3 4.8.4 4.9 4.10 4.11 4.12
Programming the Display Timing...................................................................................36 Panel Power Sequencing (PPWR, PBIAS) .....................................................................37 Output Dithering .............................................................................................................38 Four Channel LVDS Transmitter (for GMZAN3L Only) ....................................................38 Flexible TTL Outputs (GMZAN3T Only)............................................................................39 Energy Spectrum Management (ESM)................................................................................39 OSD .....................................................................................................................................39 On-Chip OSD SRAM .................................................................................................40 Color Look-up Table (LUT) .......................................................................................41
4.12.1 4.12.2 4.13 4.14 4.15
General Purpose Inputs and Outputs (GPIO's) ...................................................................41 Bootstrap Configuration Pins ..............................................................................................41 Host Interface ......................................................................................................................41 Host Interface Command Format - for 2 or 6-wire ....................................................42 2-wire Serial Protocol .................................................................................................42 8-bit Parallel Interface ................................................................................................44 Low Power State.........................................................................................................45 Pulse Width Modulation (PWM) Back Light Control ................................................45
4.15.1 4.15.2 4.15.3 4.16 4.16.1 4.16.2 5 5.1 5.2 6 7
Miscellaneous Functions .....................................................................................................45
Electrical Specifications ...............................................................................................................46 Preliminary DC Characteristics ...........................................................................................46 Preliminary AC Characteristics ...........................................................................................49
Ordering Information ...................................................................................................................52 Mechanical Specifications............................................................................................................53
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GMZAN3 Preliminary Data Sheet
List Of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28.
Analog Input Port (Common to GMZAN3T and GMZAN3L) .............................................12 Clock Pins (Common to GMZAN3T and GMZAN3L).........................................................12 System Interface and GPIO Signals (GMZAN3T) ...............................................................13 System Interface and GPIO Signals (GMZAN3L) ...............................................................14 Display Output Port for (GMZAN3L)..................................................................................15 Display Output Port for (GMZAN3T)..................................................................................16 Reserved Pins for GMZAN3L..............................................................................................17 Reserve Pins for GMZAN3T................................................................................................17 I/O Power and Ground Pins for GMZAN3L ........................................................................17 Power and Ground Pins for LVDS Transmitter for GMZAN3L......................................18 I/O Power and Ground pins for GMZAN3T ....................................................................18 TCLK Specification ........................................................................................................22 Temperature and Voltage variations for TRESETn..........................................................26 Pin Connection for RGB Input with HSYNC/VSYNC...................................................26 ADC Characteristics........................................................................................................28 Temperature and Voltage Variation for Schmitt Trigger ................................................30 Supported LVDS 24-bit Panel Data Mappings ...............................................................39 Supported LVDS 18-bit Panel Data Mapping.................................................................39 Bootstrap Signals.............................................................................................................41 Instruction Byte Map.......................................................................................................42 Absolute Maximum Ratings............................................................................................46 GMZAN3L DC Characteristics........................................................................................47 GMZAN3T DC Characteristics........................................................................................48 Maximum Speed of Operation ........................................................................................49 Display Timing and DCLK Adjustments........................................................................49 2-Wire Host Interface Port Timing .................................................................................49 Microcontroller Interface Timing (Muxed Address/Data) for Register Read/Write.......50 Microcontroller Interface Timing (Muxed Address/Data) for OSD Memory Read/Write51
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GMZAN3 Preliminary Data Sheet
List Of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. GMZAN3 System Design Examples..................................................................................8 GMZAN3T Pin Out Diagram...........................................................................................10 GMZAN3L Pin out Diagram............................................................................................11 GMZAN3 Functional Block Diagram ..............................................................................19 Using the Internal Oscillator with External Crystal ........................................................20 Internal Oscillator Output................................................................................................21 Sources of Parasitic Capacitance.....................................................................................22 Using an External Single-ended Clock Oscillator...........................................................22 Internally Synthesized Clocks .........................................................................................23 GMZAN3 Re-setting External MCU................................................................................25 External MCU Re-setting GMZAN3................................................................................25 Reset Signal Timing (TRESETn).......................................................................................25 Example ADC Signal Terminations................................................................................27 GMZAN3 Clock Recovery...............................................................................................29 Schmitt Trigger Timing Diagram....................................................................................30 Supported SOG and CSYNC signals ..............................................................................31 ADC Capture Window ....................................................................................................32 Some of GMZAN3 built-in test patterns ..........................................................................32 Factory Calibration and Test Environment .....................................................................33 ODD/EVEN Field Detection...........................................................................................34 Display Windows and Timing.........................................................................................36 Single Pixel Width Display Data.....................................................................................37 Double Pixel Wide Display Data ....................................................................................37 Panel Power Sequencing .................................................................................................38 OSD Cell Map.................................................................................................................40 2-Wire Protocol Data Transfer ........................................................................................43 2-Wire Write Operations (0x1x and 0x2x)......................................................................43 2-Wire Read Operation (0x9x and 0xAx) .......................................................................44 8-bit Parallel Interface .....................................................................................................44 Microcontroller Register Write Cycle.............................................................................50 Microcontroller Register Read Cycle..............................................................................51 Microcontroller OSD CCF Write Cycle..........................................................................52 Microcontroller OSD CCF Read Cycle...........................................................................52 GMZAN3 128-pin PQFP Mechanical Drawing ...............................................................53
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GMZAN3 Preliminary Data Sheet
Revision History
Document
C0523-DAT-01A C0523-DAT-01B C0523-DAT-01C
Description
* * * * * * * * * * Initial Release
Date
Feb. 2003 Mar. 2003
Changed the LVDS pin names to allow simple board layout. See Figure 3 and Table 5. Feb. 2003 Fixed typo in Table 19 VVDD_1.85 >> VVDD_1.8. Updated Table 20 with correct 1.8V voltage min and max Updated the minimum and maximum operating conditions in Section 5.2 Preliminary AC Characteristics.
C0523-DAT-01D
Removed Dual- edge clocking from section 4.11 Apr. 2003 Updated Table 19 with Theta Jc and Theta Ja values Updated Table 20 with measured Power consumption for GMZAN3L Added Table 21 with GMZAN3T DC characteristics with measured Power Consumption Added information on the integrated Reset Circuit * Figure 10 GMZAN3 Re-setting external MCU * Figure 11 External MCU re-setting GMZAN3 * Figure 12 Reset Signal Timing * Table 13 Temperature & Voltage Variation on the Reset Circuit Added Section 4.3.5 on the Schimtt Trigger * Figure 15 Schmitt Trigger Timing * Table 16 Temperature & Voltage Variation on the Schimtt Trigger Changed Figure 14 drawing with more clarification Pin corrections (documentation error): * GMZAN3L - corrected pins: 40, 43, 52,53, 60, 63 (GPIO[8:13] to GPO[8:13]) * GMZAN3T - corrected pins: 40, 43, 52, 53, 60, 63 Part Number change: removed hyphen from chip name throughout document Updated frequency in TCLK specification table. Corrected storage temperature in Preliminary DC Characteristics Updated Table 16 Temperature and Voltage variation of the Schmitt trigger
C0523-DAT-01E
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C0523-DAT-01F
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May 2003
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GMZAN3 Preliminary Data Sheet
1 Overview
The GMZAN3 is a graphics processing IC for Liquid Crystal Display (LCD) monitors at XGA resolution. It provides all key IC functions required for the highest quality LCD monitors. On-chip functions include a high-speed triple-ADC and PLL, a high quality zoom and shrink scaling engine, an on-screen display (OSD) controller and digital color controls. The GMZAN3 is provided with two versions;
*
*
GMZAN3T with 48-bit TTL output and
GMZAN3L with industry standard single four channel LVDS transmitter for direct connect to LCD panels with LVDS interface.
With this level of integration, the GMZAN3 devices simplify and reduce the cost of LCD monitors while maintaining a high-degree of flexibility and quality.
1.1 GMZAN3 System Design Examples
Figure 1 below shows a typical analog interface LCD monitor system based on the GMZAN3. The GMZAN3 reduces system cost, simplifies hardware and firmware design and increased reliability because only a minimal number of components are required in the system.
Direct Connect to LVDS IF for Panels Analog RGB
GMZAN3T/L
LCD Module
TTL IF to Panels
Back-light
Micro
Figure 1.
GMZAN3 System Design Examples
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GMZAN3 Preliminary Data Sheet
1.2 GMZAN3 Features
FEATURE OVERVIEW
* * * * * * * * * * Zoom (from VGA) and shrink (from SXGA) scaling Integrated 8-bit triple-channel ADC / PLL Csync and SOG support On-chip versatile OSD engine All system clocks synthesized from a single external crystal On-chip reset circuit Programmable gamma correction (CLUT) PWM back light intensity control 5-Volt tolerant inputs - up to 13 GPIO pins Low EMI and power saving features
Built in Test Pattern Generator
* Simplifies manufacturing and testing
Highly Integrated Solution to Provide Low System Cost
* * * * Two layer PCB support On-chip reset feature to eliminate external reset component Output slew rate control Integrated Schmitt trigger for Vsync and Hsync
OUTPUT INTERFACE
High-Quality Advanced Scaling
* * * Fully programmable zoom ratios Shrink capability from SXGA resolution Real Recovery function provides full color recovery image for refresh rates higher than those supported by the LCD panel
GMZAN3T
* * * * * Support for 8 or 6-bit panels (with high-quality dithering) Swap red and green channels Ability to reverse bit order of each R, G, B output Single or double pixel clock Support up to XGA 85Hz
Analog RGB Input Port
* * Supports up to SXGA input On-chip high-performance PLLs (only a single reference crystal required)
Built in Flexible LVDS Transmitter for GMZAN3L
* * * Four channel 6/8-bit LVDS transmitter (with high-quality dithering) Programmable channel swapping and polarity Support up to XGA 85Hz output
Auto-Configuration / Auto-Detection
* * Automatic input format detection Robust phase and image positioning
On-Chip OSD Controller
* * * * * * On-chip RAM for downloadable menus 1 and 2-bit per pixel character cells Horizontal and vertical stretch of OSD menus Blinking and transparency Proportional font support 90 degree rotation of fonts for Portrait Display support
PACKAGE
* 128-pin PQFP
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GMZAN3 Preliminary Data Sheet
2 GMZAN3 Pinout
These devices are available in a 128-pin Plastic Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals.
HDATA0/AD0/HP0 HDATA1/AD1/HP1 HDATA2/AD2/OSC_SEL HDATA3/AD3 HFS/AD4 GPIO7/AD5 GPIO6/AD6 GPIO5/AD7 RDn WRn HCLK/ALE GPIO4/MEM_REG GPIO3/IRQn CRVSS CVDD_1.8 CRVSS RVDD_3.3 TCLK XTAL AVDD_RPLL_3.3 AVSS_RPLL VBUFS_RPLL VDD_RPLL_1.8 VSS_RPLL VDD_ADC_1.8 GND_ADC 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
Figure 2.
C0523-DAT-01G
PD23/EB7 PD24/OR0/GPO12 RVDD_3.3 CRVSS PD25/OR1/GPO13 PD26/OR2 PD27/OR3 PD28/OR4 PD29/OR5 PD30/OR6 CVDD_1.8 CRVSS PD31/OR7 PD32/OG0/GPO10 PD33/OG1/GPO11 PD34/OG2 PD35/OG3 PD36/OG4 PD37/OG5 PD38/OG6 PD39/OG7 PD40/OB0/GPO8 RVDD_3.3 CRVSS PD41/OB1/GPO9 PD42/OB2
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
RESETn RESET_OUT VCO_LV AVDD_3.3 AVSS PD0/ER0 PD1/ER1 PD2/ER2 PD3/ER3 PD4/ER4 PD5/ER5 PD6/ER6 PD7/ER7 PD8/EG0 PD9/EG1 AVSS AVDD_3.3 AVSS AVDD_3.3 CVDD_1.8 CRVSS RVDD_3.3 CRVSS PD10/EG2 PD11/EG3 PD12/EG4 PD13/EG5 PD14/EG6 PD15/EG7 PD16/EB0 PD17/EB1 PD18/EB2 PD19/EB3 PD20/EB4 CVDD_1.8 CRVSS PD21/EB5 PD22/EB6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AGND_ADC ADC_TEST AVDD_ADC_3.3 AGND_RED REDRED+ AVDD_RED_3.3 AGND_GREEN GREENGREEN+ SOG_MCSS AVDD_GREEN_3.3 AGND_BLUE BLUEBLUE+ AVDD_BLUE_3.3 VSYNC HSYNC STI_TM2 STI_TM1 CRVSS CVDD_1.8 GPIO0/PWM0 GPIO1/PWM1 GPIO2 PBIAS CRVSS RVDD_3.3 PPWR DCLK DVS DHS DEN PD47/OB7 PD46/OB6 PD45/OB5 PD44/OB4 PD43/OB3
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GMZAN3T
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GMZAN3T Pin Out Diagram
July 2003
GMZAN3 Preliminary Data Sheet
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
HDATA0/AD0/HP0 HDATA1/AD1/HP1 HDATA2/AD2/OSC_SEL HDATA3/AD3 HFS/AD4 GPIO7/AD5 GPIO6/AD6 GPIO5/AD7 RDn WRn HCLK/ALE GPIO4/MEM_REG GPIO3/IRQn CRVSS CVDD_1.8 CRVSS RVDD_3.3 TCLK XTAL AVDD_RPLL_3.3 AVSS_RPLL VBUFS_RPLL VDD_RPLL_1.8 VSS_RPLL VDD_ADC_1.8 GND_ADC
Figure 3.
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RESERVED GPO12 RVDD_3.3 CRVSS GPO13 RESERVED RESERVED RESERVED RESERVED RESERVED CVDD_1.8 CRVSS RESERVED GPO10 GPO11 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED GPO8 RVDD_3.3 CRVSS GPO9 RESERVED
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
RESETn RESET_OUT VCO_LV AVDD_OUT_LV_3.3 AVSS_OUT_LV CH3P_LV CH3N_LV CLKP_LV CLKN_LV CH2P_LV CH2N_LV CH1P_LV CH1N_LV CH0P_LV CH0N_LV AVSS_OUT_LV AVDD_OUT_LV_3.3 AVSS_LV AVDD_LV_3.3 CVDD_1.8 CRVSS RVDD_3.3 CRVSS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CVDD_1.8 CRVSS RESERVED RESERVED
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AGND_ADC ADC_TEST AVDD_ADC_3.3 AGND_RED REDRED+ AVDD_RED_3.3 AGND_GREEN GREENGREEN+ SOG_MCSS AVDD_GREEN_3.3 AGND_BLUE BLUEBLUE+ AVDD_BLUE_3.3 VSYNC HSYNC STI_TM2 STI_TM1 CRVSS CVDD_1.8 GPIO0/PWM0 GPIO1/PWM1 GPIO2 PBIAS CRVSS RVDD_3.3 PPWR DCLK DVS DHS DEN RESERVED RESERVED RESERVED RESERVED RESERVED
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GMZAN3L
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GMZAN3L Pin out Diagram
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GMZAN3 Preliminary Data Sheet
3 GMZAN3 Pin List
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground, I-PU = Input with pull-up, I-PD = Input with pull down, IO-PD = Bidirectional with pull down Table 1.
Analog Input Port (Common to GMZAN3T and GMZAN3L)
Pin Name
AVDD_RED_3.3 RED+ REDAGND_RED AVDD_GREEN_3.3 SOG_MCSS GREEN+ GREENAGND_GREEN AVDD_BLUE_3.3 BLUE+ BLUEAGND_BLUE AVDD_ADC_3.3
No.
96 97 98 99 91 92 93 94 95 87 88 89 90 100
I/O
AP AI AI AG AP AI AI AI AG AP AI AI AG AP
Description
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor (0.1F) to AGND_RED pin on system board (as close as possible to the pin). Positive analog input for Red channel. Negative analog input for Red channel. Analog ground for the red channel. Must be directly connected to the system ground plane. Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor (0.1F) to AGND_GREEN pin on system board (as close as possible to the pin). Dedicated Sync-on-Green pin Positive analog input for Green channel. Negative analog input for Green channel. Analog ground for the green channel. Must be directly connected to the system ground plane. Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor (0.1F) to AGND_BLUE pin on system board (as close as possible to the pin). Positive analog input for Blue channel. Negative analog input for Blue channel. Analog ground for the blue channel. Must be directly connected to the system ground plane. Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes band gap reference, master biasing and full-scale adjust. Must be bypassed with decoupling capacitor (0.1F) to AGND_ADC pin on system board (as close as possible to the pin). Analog test output for ADC. Do not connect. Analog ground for ADC analog blocks that are shared by all three channels. Includes band gap reference, master biasing and full-scale adjust. Must be directly connected to system ground plane. Digital ground for ADC clocking circuit. Must be directly connected to the system ground plane. Digital power (1.8V) for ADC encoding logic. Must be bypassed with decoupling capacitor (0.1F) to GND_ADC pin on system board (as close as possible to the pin). ADC input horizontal sync input. The input hysteresis can be set to 0.5V or 1.5V [Input, Schmitt trigger, 5V-tolerant] ADC input vertical sync input. The input hysteresis can be set to 0.5V or 1.5V [Input, Schmitt triggered, 5V-tolerant]
ADC_TEST AGND_ADC
101 102
AO AG
GND_ADC VDD_ADC_1.8 HSYNC VSYNC
103 104 85 86
AG P I I
Table 2.
Clock Pins (Common to GMZAN3T and GMZAN3L)
Pin Name
TCLK XTAL VBUFS_RPLL AVSS_RPLL VSS_RPLL VDD_RPLL_1.8 AVDD_RPLL_3.3
No
111 110 107 108 105 106 109
I/O
AI AO AO G G P P
Description
Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 5), or from singleended CMOS/TTL clock oscillator (see Figure 8). This is a 5V-tolerant input. See Table 14. Crystal oscillator output. Reserved. For test purposes only. Do not connect Analog ground for the reference DDS PLL. Must be directly connected to the system ground plane. Digital ground for the RCLK and clock generator. Must be directly connected to the system ground plane. Digital power for the RCLK and clock generators. Connect to 1.8V supply. Must be bypassed with a 0.1Fcapacitor to pin AVSS_RPLL Analog power for the reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a 0.1Fcapacitor to pin VSS_RPLL
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Table 3.
System Interface and GPIO Signals (GMZAN3T)
Pin Name
RESETn
No
1
I/O
IO
Description
Active-low hardware reset signal. The reset signal is held low for at least 150ms on the chip power up. It has an internal 60Kl pull-up resistor which can be used for re-setting other system devices. See section 4.2 [Bi-directional (open drain), 5V-tolerant] Active-high hardware reset signal. The reset signal is held high for at least 150ms on the chip power up. It can be used for re-setting other system devices[Output, open-drain 5Vtolerant] General-purpose input/output signal or PWM0. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal or PWM1. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal. This is also active-low interrupt input external microcontroller. [Bi-directional, Active low open drain, 5V-tolerant] General-purpose input/output signal. Open drain option via register setting. For 8-bit A/D host interface, this selects between OSD memory (high) and register access (low). [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] General-purpose input/output signal or Adddress/data[7] for 8-bit A/D host interface. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal or Adddress/data[6] for 8-bit A/D host interface. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal or Adddress/data[5] for 8-bit A/D host interface. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose output signal. GPO or TTL 48-bit panel data/Odd Blue0. General-purpose output signal. GPO or TTL 48-bit panel data/Odd Blue1. General-purpose output signal. GPO or TTL 48-bit panel data/Odd Green0. General-purpose output signal. GPO or TTL 48-bit panel data/Odd Green1. General-purpose output signal. GPO or TTL 48-bit panel data/Odd Red0. General-purpose output signal. GPO or TTL 48-bit panel data/Odd Red1. Host data for 6-wire serial protocol. For 8-bit A/D host interface determines A/D0 and A/D1 bit. Note: See Table 19, Boostrap Signals [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] If using 6-wire protocol the HDATA[2] determines bit 2 of the host data. For 8-bit A/D host interface determines A/D2 bit. Note: See Table 19, Boostrap Signals [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] If using 6-wire protocol the HDATA[3] determines the upper A/D3 bits of the host data. For 8-bit A/D host interface determines address/data bit. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] Host Frame Sync. Frames the packet on the serial channel 6-wire interface. For 8-bit A/D host interface determines A/D4 bit. [Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V-tolerant] Clock signal input for the 6-wire interface and 2-wire modes. For 8-bit A/D host interface it becomes the Address Latch Enable. [Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] For 8-bit A/D host interface write strobe input. Internal 60K pull-up. For 8-bit A/D host interface read strobe input. Internal 60K pull-up
RESET_OUT
2
O
GPIO0/PWM0 GPIO1/PWM1 GPIO2 GPIO3/IRQn
80 79 78 116
IO IO IO IO
GPIO4/MEM_REG
117
IO-PD
GPIO5/AD7
121
IO
GPIO6/AD6 GPIO7/AD5 GPO8/PD40/OB0 GPO9/PD41/OB1 GPO10/PD32/OG0 GPO11/PD33/OG1 GPO12/PD24/OR0 GPO13/PD25/OR1 HDATA0/ADO/HP0 HDATA1/AD1/HP1
122 123 60 63 52 53 40 43 128 127
IO IO O O O O O O IO-PD
HDATA2/AD2/OSC_SEL
126
IO-PD
HDATA3/AD3
125
IO-PD
HFS/AD4
124
IO
HCLK/ALE
118
I
WRn RDn
119 120
I-PU I-PU
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GMZAN3 Preliminary Data Sheet
Table 4.
System Interface and GPIO Signals (GMZAN3L)
Pin Name
RESETn
No
1
I/O
IO
Description
Active-low hardware reset signal. The reset signal is held low for at least 150ms on the chip power up. It has an internal 60Kl pull-up resistor which can be used for re-setting other system devices. See section 4.2 [Bi-directional (open drain), 5V-tolerant] Active-high hardware reset signal. The reset signal is held high for at least 150ms on the chip power up. It can be used for re-setting other system devices[Output, 5V-tolerant] General-purpose input/output signal or PWM0. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal or PWM1. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal. This is also active-low interrupt input external microcontroller. [Bi-directional, Active low open drain, 5V-tolerant] General-purpose input/output signal. Open drain option via register setting. For 8-bit A/D host interface, this selects between OSD memory (high) and register access (low). [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] General-purpose input/output signal or Adddress/data[7] for 8-bit A/D host interface. Open drain option via register setting. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal or Adddress/data[6] for 8-bit A/D host interface. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose input/output signal or Adddress/data[5] for 8-bit A/D host interface. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] General-purpose output signal. General-purpose output signal. General-purpose output. General-purpose output signal. General-purpose output signal. General-purpose output signal. Host data for 6-wire serial protocol. For 8-bit A/D host interface determines AD0 and AD1 bit. Note: See Table 19, Boostrap Signals [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] If using 6-wire protocol the HDATA[2] determines bit 2 of the host data. For 8-bit A/D host interface determines AD2 bit. Note: See Table 19, Boostrap Signals [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] If using 6-wire protocol the HDATA[3] determines the upper AD3 bits of the host data. For 8-bit A/D host interface determines address/data bit. [Bi-directional, Schmitt trigger (400mV typical hysteresis), 5V-tolerant, internal 60K pulldown] Host Frame Sync. Frames the packet on the serial channel 6-wire interface. For 8-bit A/D host interface determines AD4 bit. [Bi-directional, Schmitt trigger (400mV typical hysteresis), slew rate limited, 5V-tolerant] Clock signal input for the 6-wire interface and 2-wire modes. For 8-bit A/D host interface it becomes the Address Latch Enable. [Input, Schmitt trigger (400mV typical hysteresis), 5V-tolerant] For 8-bit A/D host interface write strobe input. Internal 60K pull-up. For 8-bit A/D host interface read strobe input. Internal 60K pull-up.
RESET_OUT GPIO0/PWM0 GPIO1/PWM1 GPIO2 GPIO3/IRQn
2 80 79 78 116
O IO IO IO IO
GPIO4/MEM_REG
117
IO-PD
GPIO5/AD7
121
IO
GPIO6/AD6 GPIO7/AD5 GPO8 GPO9 GPO10 GPO11 GPO12 GPO13 HDATA0/ADO/HP0 HDATA1/AD1/HP1
122 123 60 63 52 53 40 43 128 127
IO IO O O O O O O IO-PD
HDATA2/AD2/OSC_SEL
126
IO-PD
HDATA3/AD3
125
IO-PD
HFS/AD4
124
IO
HCLK/ALE
118
I
WRn RDn
119 120
I-PU I-PU
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Table 5.
Display Output Port for (GMZAN3L)
Pin Name
DCLK DVS DHS DEN
No
73 72 71 70
I/O
O O O O
Description
Not required. Panel output clock. Can be used for test purposes [Tri-state output, Programmable Drive] Not required. Panel Vertical Sync. Can be used for test purposes [Tri-state output, Programmable Drive] Not required. Panel Horizontal Sync. Can be used for test purposes [Tri-state output, Programmable Drive] Not required. Panel Display Enable, which frames the output background. Can be used for test purposes [Tri-state output, Programmable Drive] Panel Bias Control (back light enable) Panel Power Control LVDS Channel 3 positive1 LVDS Channel 3 negative1 LVDS Clock positive1 LVDS Clock negative1 LVDS Channel 2 positive1 LVDS Channel 2 negative1 LVDS Channel 1 positive1 LVDS Channel 1 negative1 LVDS Channel 0 positive1 LVDS Channel 0 negative1
PBIAS PPWR CH3P_LV CH3N_LV CLKP_LV CLKN_LV CH2P_LV CH2N_LV CH1P_LV CH1N_LV CH0P_LV CH0N_LV
1
77 74 6 7 8 9 10 11 12 13 14 15
O O O O O O O O O O O O
Note: These pin names are based on having swapping enabled on the initial positive and negative LVDS signals.
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Table 6.
Display Output Port for (GMZAN3T)
Pin Name
DCLK DVS DHS DEN PBIAS PPWR PD47/OB7 PD46/OB6 PD45/OB5 PD44/OB4 PD43/OB3 PD42/OB2 PD41/OB1/GPO9 PD40/OB0/GPO8 PD39/OG7 PD38/OG6 PD37/OG5 PD36/OG4 PD35/OG3 PD34/OG2 PD33/OG1/GPO11 PD32/OG0/GPO10 PD31/OR7 PD30/OR6 PD29/OR5 PD28/OR4 PD27/OR3 PD26/OR2 PD25/OR1/GPO13 PD24/OR0/GPO12 PD23/EB7 PD22/EB6 PD21/EB5 PD20/EB4 PD19/EB3 PD18/EB2 PD17/EB1 PD16/EB0 PD15/EG7 PD14/EG6 PD13/EG5 PD12/EG4 PD11/EG3 PD10/EG2 PD9/EG1 PD8/EG0 PD7/ER7 PD6/ER6 PD5/ER5 PD4/ER4 PD3/ER3 PD2/ER2
No
73 72 71 70 77 74 69 68 67 66 65 64 63 60 59 58 57 56 55 54 53 52 51 48 47 46 45 44 43 40 39 38 37 34 33 32 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8
I/O
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
Description
Panel output clock. [Tri-state output, Programmable Drive] Panel Vertical Sync. [Tri-state output, Programmable Drive] Panel Horizontal Sync. [Tri-state output, Programmable Drive] Panel Display Enable, which frames the output background. [Tri-state output, Programmable Drive] Panel Bias Control (back light enable) Panel Power Control Panel output data or Odd Blue 7 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Blue 6 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Blue 5 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Blue 4 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Blue 3 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Blue 2 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Blue 1 data bit. [Tri-state output, Programmable Drive] When used with 6-bit panels can be used as GPO. Panel output data or Odd Blue 0 data bit. [Tri-state output, Programmable Drive] When used with 6-bit panels can be used as GPO. Panel output data or Odd Green 7 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Green 6 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Green 5 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Green 4 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Green 3 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Green 2 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Green 1 data bit. [Tri-state output, Programmable Drive] When used with 6-bit panels can be used as GPO. Panel output data or Odd Green 0 data bit. [Tri-state output, Programmable Drive] When used with 6-bit panels can be used as GPO. Panel output data or Odd Red 7 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Red 6 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Red 5 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Red 4 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Red 3 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Red 2 data bit. [Tri-state output, Programmable Drive] Panel output data or Odd Red 1 data bit. [Tri-state output, Programmable Drive] When used with 6-bit panels can be used as GPO. Panel output data or Odd Red 0 data bit. [Tri-state output, Programmable Drive] When used with 6-bit panels can be used as GPO. Panel output data or Even Blue 7 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 6 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 5 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 4 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 3 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 2 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 1 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Blue 0 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 7 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 6 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 5 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 4 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 3 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 2 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 1 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Green 0 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 7 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 6 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 5 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 4 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 3 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 2 data bit. [Tri-state output, Programmable Drive]
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GMZAN3 Preliminary Data Sheet
Pin Name
PD1/ER1 PD0/ER0
No
7 6
I/O
O O
Description
Panel output data or Even Red 1 data bit. [Tri-state output, Programmable Drive] Panel output data or Even Red 0 data bit. [Tri-state output, Programmable Drive]
Table 7.
Reserved Pins for GMZAN3L
Pin Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved VC0_LV STI_TM1 STI_TM2
No
69 68 67 66 65 64 59 58 57 56 55 54 51 48 47 46 45 44 39 38 37 34 33 32 31 30 29 28 27 26 25 24 3 83 84
I/O
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I I
Description
Do not connect Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. Do not connect. For test purposes only. Do not connect For test purposes only. Has internal 60K pull-down register. Must be connected to GND For test purposes only. Has internal 60K pull-down register. Must be connected to GND
Table 8.
Reserve Pins for GMZAN3T
Pin Name
VCO_LV STI_TM1 STI_TM2
No
3 83 84
I/O
O I-PD I-PD
Description
For test purposes only. Do not connect For test purposes only. Has internal 60K pull-down resistor. For test purposes only. Has internal 60K pull-down resistor.
Table 9.
I/O Power and Ground Pins for GMZAN3L
Pin Name
RVDD_3.3
No
22 41 61 75 112 21 23 36
I/O
P P P P P G G G
Description
Connect to 3.3V digital supply. Must be bypassed with a 0.1F capacitor to CRVSS (as close to the pin as possible).
CRVSS
Connect to digital ground.
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CVDD_1.8
42 50 62 76 82 113 115 20 35 49 81 114
G G G G G G G P P P P P
Connect to 1.8V digital supply. Must be bypassed with a 0.1F capacitor to CRVSS (as close to the pin as possible).
Table 10.
Power and Ground Pins for LVDS Transmitter for GMZAN3L
Pin Name
AVDD_OUT_LV_3.3 AVDD_LV_3.3 AVSS_OUT_LV AVSS_LV
No
4 17 19 5 16 18
I/O
AP AP G G
Description
Analog power for on-chip LVDS output buffer. Connect to 3.3V supply. Must be bypassed with a 0.1Fcapacitor to pin AVSS_OUT_LV Analog power for on-chip LVDS PLL. Connect to 3.3V supply. Must be bypassed with a 0.1Fcapacitor to pin AVSS_LV Analog ground for on-chip LVDS output buffer. Must be directly connected to the system ground plane Analog ground for on-chip LVDS PLL. Must be directly connected to the system ground plane
Table 11.
I/O Power and Ground pins for GMZAN3T
Pin Name
RVDD_3.3
No
22 41 61 75 112 21 23 36 42 50 62 76 82 113 115 20 35 49 81 114 5 16 18 4 17 19
I/O
P P P P P G G G G G G G G G G P P P P P G G G P
Description
Connect to 3.3V digital supply. Must be bypassed with a 0.1F capacitor to CRVSS (as close to the pin as possible).
CRVSS
Connect to digital ground.
CVDD_1.8
Connect to 1.8V digital supply. Must be bypassed with a 0.1F capacitor to CRVSS (as close to the pin as possible).
AVSS
Connect to digital ground
AVDD_3.3
Connect to 3.3V supply Must be bypassed with a 0.1F capacitor to ACVSS (as close to the pin as possible).
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4 Functional Description
A functional block diagram is illustrated below. Each of the functional units shown is described in the following sections.
Host I/F GPIO Crystal Reference
Reset Circuit
Host Interface
Clock Generation
OSD Controller
OSD RAMs
Energy Spectrum Manager
Analog RGB HS, VS
Triple ADC & PLL
Image Capture / Measurement
Zoom / Shrink / Filter
Gamma Control
Output Data Path
LVDS Transmitter
GMZAN3L
Single Channel LVDS Panel Data and Control
Test Pattern Generator 24/36/48-bit TTL Output
GMZAN3T
TTL output to LCD Panel
Figure 4.
GMZAN3 Functional Block Diagram
4.1 Clock Generation
The GMZAN3 features two clock inputs. All additional clocks are internal clocks derived from one or more of these: 1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and corresponding logic. A 14.318 MHz crystal is recommended. Other crystal frequencies may be used, but require custom programming. This is illustrated in Figure 5 below. This option is selected by connecting a 10K pull-up to HDATA2/AD2/OSC_SEL. Alternatively a single-ended TTL/CMOS clock oscillator can be driven into the TCLK pin (leave XTAL and HDATA2/AD2/OSC_SEL as N/C in this case). This is illustrated in Figure 8 below. See also Table 14. 2. Host Interface Transfer Clock (HCLK). For 2 or 6-wire Host Interface Port only. Not for muxed A/D. The GMZAN3 TCLK oscillator circuitry is a custom designed circuit to support the use of an external oscillator or a crystal resonator to generate a reference frequency source for the GMZAN3 device. 4.1.1 Using the Internal Oscillator with External Crystal
The first option for providing a clock reference is to use the internal oscillator with an external crystal. The oscillator circuit is designed to provide a very low jitter and very low harmonic clock to the internal circuitry of the GMZAN3. An Automatic Gain Control (AGC) is used to insure startup and operation over
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GMZAN3 Preliminary Data Sheet
a wide range of conditions. The oscillator circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal. When the GMZAN3 is in reset, the state of the HDATA2/AD2/OSC_SEL pin is sampled. If the pin is pulled high by connecting to VDD through a pull-up resistor (10K recommended, 15K maximum) then internal oscillator is enabled. In this mode a crystal resonator is connected between TCLK and the XTAL with the appropriately sized loading capacitors CL1 and CL2. The size of CL1 and CL2 are determined from the crystal manufacturer's specification and by compensating for the parasitic capacitance of the GMZAN3 device and the printed circuit board traces. The loading capacitors are terminated to the analog VDD power supply. This connection increases the power supply rejection ratio when compared to terminating the loading capacitors to ground.
Vdda
GMZAN3
CL1
111 Vdd TCLK
110 Vdda CL2 Vdda XTAL OSC_OUT TCLK Distribution 180 uA
100 K
10 K 126 Reset State Logic HDATA2/AD2/OSC_SEL Internal Pull Down Resistor ~ 60K Internal Oscillator Enable
Figure 5.
Using the Internal Oscillator with External Crystal
The TCLK oscillator uses a Pierce Oscillator circuit. The output of the oscillator circuit, measured at the TCLK pin, is an approximate sine wave with a bias of about 2 volts above ground (see Figure 6). The peak-to-peak voltage of the output can range from 250 mV to 1000 mV depending on the specific characteristics of the crystal and variation in the oscillator characteristics. The output of the oscillator is connected to a comparator that converts the sine wave to a square wave. The comparator requires a
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GMZAN3 Preliminary Data Sheet
minimum signal level of about 50-mV peak to peak to function correctly. The output of the comparator is buffered and then distributed to the GMZAN3 circuits.
3.3 Volts
~ 2 Volts
250 mV peak to peak to 1000 mV peak to peak
time
Figure 6.
Internal Oscillator Output
One of the design parameters that must be given some consideration is the value of the loading capacitors used with the crystal as shown in Figure 7. The loading capacitance (Cload) on the crystal is the combination of CL1 and CL2 and is calculated by Cload = ((CL1 * CL2) / (CL1 + CL2)) + Cshunt. The shunt capacitance Cshunt is the effective capacitance between the XTAL and TCLK pins. For the GMZAN3 this is approximately 9 pF. CL1 and CL2 are a parallel combination of the external loading capacitors (Cex), the PCB board capacitance (Cpcb), the pin capacitance (Cpin), the pad capacitance (Cpad), and the ESD protection capacitance (Cesd). The capacitances are symmetrical so that CL1 = CL2 = Cex + CPCB + Cpin + Cpad + CESD. The correct value of Cex must be calculated based on the values of the load capacitances. Approximate values are provided in Figure 7.
CL1 = Cex1 + Cpcb + Cpin + Cpad + Cesd
Vdda
Cex1
Cpcb
111 TCLK
Cpin
Cpad
Cesd Internal Oscillator
GMZAN3 Cshunt 110 XTAL Cpcb Cpin Cpad Cesd
Vdda
Cex2
CL2 = Cex1 + Cpcb + Cpin + Cpad + Cesd
Approximate values: CPCB ~ 2 pF to 10 pF (layout dependent) Cpin ~ 1.1 pF Cpad ~ 1 pF Cesd ~ 5.3 pF Cshunt ~ 9 pF
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Figure 7.
Sources of Parasitic Capacitance
Some attention must be given to the details of the oscillator circuit when used with a crystal resonator. The PCB traces should be as short as possible. The value of Cload that is specified by the manufacturer should not be exceeded because of potential start up problems with the oscillator. Additionally, the crystal should be a parallel resonate-cut and the value of the equivalent series resistance must be less then 90 Ohms. 4.1.2 Using an External Clock Oscillator
Another option for providing the reference clock is to use a single-ended external clock oscillator. When the GMZAN3 is in reset, the state of the HDATA2/AD2/OSC_SEL is sampled. If the pin is left unconnected (internal pull-down) then external oscillator mode is enabled. In this mode the internal oscillator circuit is disabled and the external oscillator signal that is connected to the TCLK pin is routed to an internal clock buffer. This is illustrated in Figure 8.
Vdd
14 to 24 MHz 111
GMZAN3
Vdd Oscillator GND 110 XTAL Internal Oscillator Disable TCLK OSC_OUT TCLK Distribution
126 HDATA2/AD2/OSC_SEL
Reset State Logic External Oscillator Enable
10K (OPTIONAL)
Internal Pull Down Resistor ~ 60 K
Figure 8.
Using an External Single-ended Clock Oscillator
Table 12.
Frequency Jitter Tolerance Rise Time (10% to 90%) C0523-DAT-01G
TCLK Specification
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GMZAN3 Preliminary Data Sheet
Maximum Duty Cycle
40-60
4.1.3
Clock Synthesis
The GMZAN3 synthesizes all additional clocks internally as illustrated in Figure 9 below. The synthesized clocks are as follows: 1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from the TCLK/XTAL pad input. 2. Reference Clock (RCLK) synthesized by RCLK PLL (RPLL) using TCLK as the reference. 3. Input Source Clock (SCLK) synthesized by Source DDS (SDDS) PLL using input HSYNC as the reference. The SDDS internal digital logic is driven by RCLK. 4. ADC Output Clock (ACLK) is a delay-adjusted ADC sampling clock, ACLK. ACLK is derived from SCLK. 5. Host Port Clock for OSD SRAM and muxed A/D port. TCLK at power up, and selectable as RCLK/2 or RCLK/4.
HSYNC
SDDS
ACLK DCLK
SCLK TCLK
RCLK PLL
DDDS
/4 /2 M U X
HOST_CLK
for muxed A/D 8051 interface
Figure 9.
Internally Synthesized Clocks
The on-chip clock domains are selected from the synthesized clocks. These include: 1. ADC Domain Clock (ACLK) which is also the input clock. Max = 100MHz 2. Host Interface (HOST_CLK). Max = 120MHz 3. Scaler and Display Pixel Clock (DP_CLK). Max = 100MHz 4. Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz
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4.2 Hardware Reset
Hardware Reset is performed during power-up by the internal power-on reset circuit. The power-on reset (POR) circuit generates two signals: * * RESETn: an active-low pulse of around 120ms RESET_OUT: an active-high pulse with identical timing as RESETn; this is basically an inverted version of RESETn. Must use 10K pull-up resistor because this is an open-drain output.
The reset signals are generated whenever the supply 3.3V voltage reaches a voltage level of +2.5V, or if the RESETn pin is pulled low for a minimum of 160 us. A TCLK input (see Clock Requirements below) must be applied before, during, and after the reset. While RESETn is active low, pins PD[47:10] DEN, DHS, DVS, and DCLK are all HI-Z; HDATA [3:0], GPIO[7:0] and HFS are inputs; PBIAS and PPWR are active outputs (0 after reset is complete). When the reset period is complete and RESETn is deasserted, the IC power up sequence is: 1. Reset all registers to their default state (this is 00h unless otherwise specified in the GMZAN3 Register Listing). 2. Force each clock domain to reset. Internal reset will remain asserted for 64 local clock domain cycles following the de-assertion of RESETn. The following figures illustrate different system configuration options of the GMZAN3 POR circuit: 1. In figure 10, the GMZAN3 RESET_OUT signal resets the external MCU during power-up. An optional push button allows the user to reset the entire system. 2. In figure 11, an external MCU generates the reset, applied to RESETn input of GMZAN3.
+ 3 .3 V / + 5 V + 3 .3 V
10K RESET_O UT 2
gm ZAN 3
RST
IN T E R N A L RESET
MCU
R1 Power On R eset (P O R )
R2 V2 6K RESETn 1
DELAY
V1
O P T IO N A L A s ta b le M u ltiv ib r a to r
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Figure 10.
GMZAN3 Re-setting External MCU
+3.3V
RESET_OUT (NC)
2
gm ZAN3
INTERNAL RESET
R1 Power On Reset (POR)
R2 V2
MCU
+3.3V / +5V RESETn 10K 1
6K
DELAY
V1 I/O PORT
Astable Multivibrator
Figure 11.
External MCU Re-setting GMZAN3
Voltage drop Threshold = +2.5V +3.3V_AVDD
TRESETn
TRESETn
RESETn
RESET_OUT
Figure 12.
Reset Signal Timing (TRESETn)
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Note: * * * * The RESETn pin may also be connected to an external momentary contact switch to ground, for a Reset Button feature. When analog 3.3V reaches the reset threshold (2.5V) an active LOW reset signal is generated (RESETn). The duration of the reset pulse is about 120ms. The RESET_OUT is active HIGH output pulse held high while RESETn is LOW When +3.3V_AVDD drops below 2.5V a reset signal is generated. The reset signal gets de-asserted about 120ms after the input voltage rises above the 2.5V threshold (see figure 12). The following table shows the temperature/voltage variation effects on the RESETn timing (TRESETn).
Table 13. Voltage 3.0V 3.3V 3.6V
*
Temperature and Voltage variations for TRESETn
0C 107 ms 119 ms 123 ms Room Temperature 105 ms 118 ms 123 ms 100C 110 ms 119 ms 126 ms
4.3 Analog to Digital Converter
The GMZAN3chip has three ADC's (analog-to-digital converters), one for each color (red, green, and blue). 4.3.1 ADC Pin Connection
The analog RGB signals are connected to the GMZAN3 as described below:
Table 14. Pin Name Red+ RedSOG_MCSS Green+ GreenBlue+ BlueHSYNC VSYNC
Pin Connection for RGB Input with HSYNC/VSYNC
ADC Signal Name Red Terminate as illustrated in Figure 13 Dedicated Sync-on-Green pin (for sync-tip clamping) Green Terminate as illustrated in Figure 13 Blue Terminate as illustrated in Figure 13 Horizontal Sync (Terminate as illustrated in Figure 13) Vertical Sync (Terminate as with HSYNC illustrated in Figure 13)
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RED + 0.01uF 75
RED RED
0.01uF
GMZAN3
SOG_MCSS
GREEN
GREEN
0.01uF DB15
BLUE
75 0.01uF
GREEN +
Hsync Vsync
GREEN 0.01uF
BLUE +
GND
0.01uF 75
BLUE 0.01uF
HSYNC
HS VS
VSYNC
Figure 13.
Example ADC Signal Terminations
NOTE: It is very important to follow the recommended layout guidelines for the circuit shown in Figure 13. Follow the recommendations in the GMZAN3 Layout Guidelines. For specific component values refer to the GMZAN3 RD1 Reference Design Schematics.
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4.3.2
ADC Characteristics
The table below summarizes the characteristics of the ADC:
Table 15.
MIN
Track & Hold Amp Bandwidth
ADC Characteristics
MAX NOTE
290 MHz Guaranteed. Note that the Track & Hold Amp Bandwidth is programmable. 290 MHz is the maximum setting. 0.90 V Measured at ADC Output. Independent of full scale RGB input. Measured at ADC Output. 100 MHz +/-0.9 LSB Fs = 100 MHz Guaranteed by test. Fs =100 MHz
TYP
Full Scale Adjust Range at RGB Inputs Full Scale Adjust Sensitivity Zero Scale Adjust Sensitivity Sampling Frequency (Fs) Differential Non-Linearity (DNL) No Missing Codes Integral Non-Linearity (INL) Channel to Channel Matching
0.55 V +/- 1 LSB +/- 1 LSB 10 MHz +/-0.5 LSB +/- 1.5 LSB +/- 0.5 LSB
Note that input formats with resolutions or refresh rates higher than that supported by the LCD panel are supported as recovery modes only. This is called RealRecoveryTM. For example, it may be necessary to shrink the image. This may introduce image artifacts. However, the image is clear enough to allow the user to change the display properties. The GMZAN3 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors (about 10 nF), the DC offset of an external video source can be removed. The clamp pulse position and width are programmable. 4.3.3 Clock Recovery Circuit
The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample analog RGB data (ACLK). This circuit is locked to HSYNC of the incoming video signal. Patented digital clock synthesis technology makes the GMZAN3 clock circuits resistant to temperature/voltage drift. Using DDS (Direct Digital Synthesis) technology, the clock recovery circuit can generate any ACLK clock frequency within the range of 10 MHz to 100 MHz.
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BLUE B G R RED GREEN
ACLK HS SCLK ACLK input HS
SDDS SCLK
Phase Delay
Input Analog Video
Input HSync SCLK ACLK Phase Delay
Figure 14.
GMZAN3 Clock Recovery
4.3.4
Sampling Phase Adjustment
The programmable ADC sampling phase is adjusted by delaying the (input HSYNC aligned) SCLK to produce the ADC clock (ACLK) inside the SDDS. The phase delay is programmable in 64 steps as a fraction of the ACLK period. The accuracy of the sampling phase is checked and the result read from a register. This feature enables accurate auto-adjustment of the ADC sampling phase. 4.3.5 Integrated Schmitt Trigger for Horizontal and Vertical Sync input
The GMZAN3 has integrated Schmitt triggers for Horizontal and Vertical Sync inputs, pin 85 and pin 86. This allows for less number of components on the system board. It enables easier PCB layout, more reliability and results in reducing the overall BOM cost. The programmable hysteresis value is either 0.5V or 1.5V
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ViH Input to Schmitt trigger ViL
Frequecy is 100KHz Hysteresis = ViH - ViL
Schmitt trigger output
Figure 15.
Table 16.
Schmitt Trigger Timing Diagram
Temperature and Voltage Variation for Schmitt Trigger
High hysteresis (0x1E7[7]=0) Default High Threshold ViH(V) 2.3 2.15 2.6 Low Threshold ViL(V) 1.0 0.9 1.1 Hysteresis ViH-ViL(V) 1.3 1.25 1.5
Room Temp @ 3.3V 100C @ 3.0V 0C @ 3.6V
NOTE: The power on default value of the hysteresis is set to high
Low hysteresis (0x1E7[7]=1) High Threshold ViH(V) 1.6 1.5 1.7 Low Threshold ViL(V) 0.9 0.8 1 Hysteresis ViH-ViL(V) 0.7 0.7 0.7
Room Temp @ 3.3V 100C @ 3.0V 0C @ 3.6V
4.3.6
SOG and CSYNC support
The GMZAN3 has the capability to support the following types of SOG and CSYNC inputs without having to use external components. The signals below show the Negative types of SOG and CSYNC signals. The GMZAN3 can also support the Positive types.
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XOR - CSYNC
NOR - CSYNC: OFF SERRATION: OFF
SERRATED (1.0H)
SERRATED (0.5 H)
Figure 16.
Supported SOG and CSYNC signals
4.3.7
ADC Capture Window
Figure 17 below illustrates the capture window used for the ADC input. In the horizontal direction the capture window is defined in ACLKs (equivalent to a pixel count). In the vertical direction it is defined in lines. All the parameters beginning with "Source" are programmed GMZAN3 registers values. Note that the input vertical total is solely determined by the input and is not a programmable parameter.
Source Horizontal Total (pixels) Reference Point Source Vstart Source Hstart
Source Width
Input Vertical Total (lines)
Source Height
Capture Window
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Figure 17.
ADC Capture Window
The Reference Point marks the leading edge of the first internal HSYNC following the leading edge of an internal VSYNC. Both the internal HSYNC and the internal VSYNC are derived from external HSYNC and VSYNC inputs. Horizontal parameters are defined in terms of single pixel increments relative to the internal horizontal sync. Vertical parameters are defined in terms of single line increments relative to the internal vertical sync. For ADC interlaced inputs, the GMZAN3 may be programmed to automatically determine the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format Measurement, Section 4.4.
4.4 Test Pattern Generator (TPG)
The GMZAN3 contains hundreds of test patterns, some of which are shown in Figure 18. Once programmed, the GMZAN3 test pattern generator can replace a video source (e.g. a PC) during factory calibration and test. This simplifies the test procedure and eliminates the possibility of image noise being injected into the system from the source. The foreground and background colors are programmable. In addition, the GMZAN3 OSD controller can be used to produce other patterns.
Figure 18.
Some of GMZAN3 built-in test patterns
The DDC port can be used for factory testing. The factory test station connects to the GMZAN3 through the Direct Data Channel (DDC) of the DSUB15 connector. Then, the PC can make GMZAN3 display test patterns (see section 4.4). A camera can be used to automate the calibration of the LCD panel.
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DDC
Factory Test Station Camera
Device-Under-Test
Figure 19.
Factory Calibration and Test Environment
4.5 Input Format Measurement
The GMZAN3 has an Input Format Measurement block (the IFM) providing the capability of measuring the horizontal and vertical timing parameters of the input video source. This information may be used to determine the video format and to detect a change in the input format. It is also capable of detecting the field type of interlaced formats. The IFM features a programmable reset, separate from the regular GMZAN3 soft reset. This reset disables the IFM, reducing power consumption. The IFM is capable of operating while GMZAN3is running in power down mode. Horizontal measurements are measured in terms of the selected IFM_CLK (either TCLK or RCLK/4), while vertical measurements are measured in terms of HSYNC pulses. For an overview of the internally synthesized clocks, see section 4.1. 4.5.1 Horizontal and Vertical Measurement
The IFM is able to measure the horizontal period and active high pulse width of the HSYNC signal, in terms of the selected clock period (either TCLK or RCLK/4.). Horizontal measurements are performed on only a single line per frame (or field). The line used is programmable. It is able to measure the vertical period and VSYNC pulse width in terms of rising edges of HSYNC. Once enabled, measurement begins on the rising VSYNC and is completed on the following rising VSYNC. Measurements are made on every field / frame until disabled. 4.5.2 Format Change Detection
The IFM is able to detect changes in the input format relative to the last measurement and then alert the system microcontroller. The microcontroller sets a measurement difference threshold separately for horizontal and vertical timing. If the current timing is different from the previously captured measurement by an amount exceeding this threshold, a status bit is set. An interrupt can also be programmed to occur.
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4.5.3
Watchdog
The watchdog monitors input VSYNC / HSYNC. When any HSYNC period exceeds the programmed timing threshold (in terms of the selected IFM_CLK), a register bit is set. When any VSYNC period exceeds the programmed timing threshold (in terms of HSYNC pulses), a second register bit is set. An interrupt can also be programmed to occur. 4.5.4 Internal Odd/Even Field Detection (For Interlaced Inputs to ADC Only)
The IFM has the ability to perform field decoding of interlaced inputs to the ADC. The user specifies start and end values to outline a "window" relative to HSYNC. If the VSYNC leading edge occurs within this window, the IFM signals the start of an ODD field. If the VSYNC leading edge occurs outside this window, an EVEN field is indicated (the interpretation of odd and even can be reversed). The window start and end points are selected from a predefined set of values.
HS window
Window Start Window End
VS - even VS - odd
Figure 20.
ODD/EVEN Field Detection
4.5.5
Input Pixel Measurement
The GMZAN3 provides a number of pixel measurement functions intended to assist in configuring system parameters such as ACLK frequency (sample clocks per line) and phase setting, centering the image, or adjusting the contrast and brightness. 4.5.6 Image Phase Measurement
This function measures the sampling phase quality over a selected active window region. This feature may be used when programming the source DDS to select the proper phase setting. 4.5.7 Image Boundary Detection
The GMZAN3 performs measurements to determine the image boundary. This information is used when programming the Active Window and centering the image. 4.5.8 Image Auto Balance
The GMZAN3 performs measurements on the input data that is used to adjust brightness and contrast.
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4.6 High-Quality Scaling
The GMZAN3 zoom scaler uses an adaptive scaling technique proprietary to Genesis Microchip Inc., and provides high quality scaling of real time video and graphics images. An input field/frame is scalable in both the vertical and horizontal dimensions. Interlaced fields may be spatially de-interlaced by vertically scaling and repositioning the input fields to align with the output display's pixel map. 4.6.1 Variable Zoom Scaling
The GMZAN3 scaling filter incorporates programmable scaling coefficients. This is useful for improving the sharpness and definition of graphics when scaling at high zoom factors (such as VGA to XGA). 4.6.2 Horizontal & Vertical Shrink
The GMZAN3 provides an arbitrary vertical shrink down to (50% + 1 pixel/line) of the original image size. The integrated ADC performs the horizontal shrink. This allows the GMZAN3 to capture and display images one VESA standard format larger than the native display resolution. For example, SXGA may be captured and displayed on an XGA panel.
4.7 Gamma LUT
The GMZAN3 provides an 8 to 10-bit look-up table (LUT) for each input color channel intended for Gamma correction and to compensate for a non-linear response of the LCD panel. A 10-bit output results in an improved color depth control. The 10-bit output is then dithered down to 8 bits (or 6 bits) per channel at the display (see section 4.8.3 below). The LUT is user programmable to provide an arbitrary transfer function. Gamma correction occurs after the zoom / shrink scaling block. The LUT has bypass enable. If bypassed, the LUT does not require programming.
4.8 Display Output Interface
The Display Output Port provides data and control signals that permit the GMZAN3 to connect to a variety of flat panel devices. The output interface is configurable for 18 or 24-bit RGB pixels, either single or double (TTL only) pixel wide. All display data and timing signals are synchronous with the DCLK output clock. 4.8.1 Display Synchronization
Refer to section 4.1 for information regarding internal clock synthesis. The GMZAN3 support the following display synchronization modes:
* Frame Sync Mode: The display frame rate is synchronized to the input frame or field rate. This mode is used for standard operation.
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*
Free Run Mode: No synchronization. This mode is used when there is no valid input timing (i.e. to display OSD messages or a splash screen) or for testing purposes. In free-run mode, the display timing is determined only by the values programmed into the display window and timing registers.
4.8.2
Programming the Display Timing
Display timing signals provide timing information so the Display Port can be connected to an external display device. Based on values programmed in registers, the Display Output Port produces the horizontal sync (DHS), vertical sync (DVS), and data enable (DEN) control signals, which are then encoded into the LVDS data stream by the on-chip LVDS transmitter. The figure below provides the registers that define the output display timing. Horizontal values are programmed in single pixel increments relative to the leading edge of the horizontal sync signal. Vertical values are programmed in line increments relative to the leading edge of the vertical sync signal.
DH_BKGND_START DH_BKGND_END
DVS
VSYNC Region Vertical Blanking (Back Porch)
DV_VS_END
Display Background Window
Horizontal Blanking (Front Porch) Horizontal Blanking (Back Porch)
DV_BKGND_START
DV_ACTIVE_START DV_TOTAL
HSYNC region
Display Active Window
DV_ACTIVE_LENGTH
DV_BKGND_END Vertical Blanking (Front Porch) DH_TOTAL
DHS DEN **
DH_HS_END DH_ACTIVE_START
DH_ACTIVE_WIDTH
** DEN is not asserted during vertical blanking
Figure 21.
Display Windows and Timing
The double-wide (TTL only) output only supports an even number of horizontal pixels.
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DCLK (Output)
DEN (Output) ER/EG/EB (Output) OR/OG/OB (Output)
XXX
rgb0
rgb1
rgb2
rgb3
rgb4
XXX
Figure 22.
Single Pixel Width Display Data
DCLK (Output)
DEN (Output) ER/EG/EB (Output) OR/OG/OB (Output)
XXX
rgb0
rgb2
rgb4
rgb6
rgb8
XXX
rgb1
rgb3
rgb5
rgb7
rgb9
Figure 23.
Double Pixel Wide Display Data
4.8.3
Panel Power Sequencing (PPWR, PBIAS)
GMZAN3 has two dedicated outputs PPWR and PBIAS to control LCD power sequencing once data and control signals are stable. The timing of these signals is fully programmable.
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TMG1
TMG2
TMG3
TMG4
PPWR Output Panel Data and Control Signals
PBIAS Output

POWER_SEQ_EN = 1
POWER_SEQ_EN = 0
Figure 24.
Panel Power Sequencing
4.8.4
Output Dithering
The Gamma LUT outputs a 10-bit value for each color channel. This value is dithered down to either 8bits for 24-bit per pixel panels, or 6-bits for 18-bit per pixel panels. The benefit of dithering is that the eye tends to average neighboring pixels and a smooth image free of contours is perceived. Dithering works by spreading the quantization error over neighboring pixels both spatially and temporally. Two dithering algorithms are available: random or ordered dithering. Ordered dithering is recommended when driving a 6-bit panel. All gray scales are available on the panel output whether using 8-bit panel (dithering from 10 to 8 bits per pixel) or using 6-bit panel (dithering from 10 down to 6 bits per pixel).
4.9 Four Channel LVDS Transmitter (for GMZAN3L Only)
The GMZAN3L implements the industry standard flexible four channel LVDS transmitter. The LVDS transmitter can support the following:
*
* * * *
Single pixel mode
24-bit panel mapping to the LVDS channels (see Table 14) 18-bit panel mapping to the LVDS channels (see Table 15) Programmable channel swapping (the clocks are fixed) Programmable channel polarity swapping
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Table 17.
Channel 0 Channel 1 Channel 2 Channel 3
Supported LVDS 24-bit Panel Data Mappings
R0, R1, R2, R3, R4, R5, G0 G1, G2, G3, G4, G5, B0, B1 B2, B3, B4, B5, PHS, PVS, PDE R6, R7, G6, G7, B6, B7, RES
Channel 0 Channel 1 Channel 2 Channel 3
R2, R3, R4, R5, R6, R7, G2 G3, G4, G5, G6, G7, B2, B3 B4, B5, B6, B7, PHS, PVS, PDE R0, R1, G0, G1, B0, B1, RES
Table 18.
Channel 0 Channel 1 Channel 2 Channel 3
Supported LVDS 18-bit Panel Data Mapping
R0, R1, R2, R3, R4, R5, G0 G1, G2, G3, G4, G5, B0, B1 B2, B3, B4, B5, PHS, PVS, PDE Disabled for this mode
4.10 Flexible TTL Outputs (GMZAN3T Only)
The GMZAN3T builds in flexibility with the ability to: * * * swap red and green channels, swap R, G, B most-significant-bit and least-significant-bit (reverse the bit-order of each R, G, B color output). output single or double pixel width data in 24 or 48 bits.
This flexibility enables the building of cost effective (2-layer) PCBs.
4.11 Energy Spectrum Management (ESM)
High spikes in the EMI power spectrum may cause LCD monitor products to violate emissions standards. The GMZAN3 has many features that can be used to reduce electromagnetic interference (EMI). These include drive strength control and clock spectrum modulation. These features help to eliminate the costs associated with EMI reducing components and shielding.
4.12 OSD
The GMZAN3 has a fully programmable, high-quality OSD controller. The OSD controller supports two independent rectangles with graphics divided into "cells" that are programmable in size (from 8 x 8 to 18 x 18 pixels). The cells are stored in an on-chip static RAM and can be stored as 1-bit per pixel data or 2bit per pixel data. This permits a good compression ratio while allowing more than 16 colors in the image. Some general features of the GMZAN3OSD controller include:
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OSD Position - The OSD menu can be positioned anywhere on the display region. The reference point is Horizontal and Vertical Display Background Start (DH_BKGND_START and DV_BKGND_START in Figure 21). OSD Stretch - The OSD image can be stretched horizontally and/or vertically by a factor of two. Pixel and line replication is used to stretch the image. 4.12.1 On-Chip OSD SRAM The on-chip static RAM (10K bytes) stores the cell map and the cell definitions. In memory, the cell map is organized as an array of words, each defining the attributes of one visible character on the screen starting from upper left of the visible character array. These attributes specify which character to display, whether it is stored as 1 or 2-bits per pixel, the foreground and background colors, blinking, etc. Registers CELLMAP_XSZ and CELLMAP_YSZ are used to define the visible area of the OSD image. For example, Figure 25 shows a cell map for which CELLMAP_XSZ =25 and CELLMAP_YSZ =10.
Address 1: Cell Attributes for upper-left hand cell Address 25: Attributes for upper-right hand cell
CELLMAP_XSZ
Address26: Cell attributes for st nd 1 cell, 2 row
CELLMAP_YSZ
Brightness Contrast
Figure 25.
OSD Cell Map
Cell font definitions are stored as bit map data. On-chip registers point to the start of 1-bit per pixel definitions and 2-bit per pixel definitions respectively. 1 and 2-bit per pixel cell definitions require 1 or 2 words of the OSD RAM per character height line. Note that the cell map and the cell font definitions share the same on-chip RAM. Thus, the size of the cell map can be traded off against the number of different cell definitions. In particular, the size of the OSD image and the number of cell definitions must fit in OSD SRAM. That is, the following inequality must be satisfied.
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CELLMAP_XSZ * CELLMAP_YSZ + CELL_HEIGHT * (Number of 1-bit per pixel fonts) + CELL_HEIGHT * (Number of 2-bit per pixel fonts) * 2
< 5120
For example, an OSD menu 360 pixels wide by 360 pixels high is 30 cells in width and 20 cells in height (if each cell is defined as 12 pixels wide and 18 lines high). Many of these cells would be the same (e.g. empty). In this case, the menu could contain 51 1-bit per pixel cells and 100 2-bit per pixel cells. Of course, different numbers of each type can also be used. 4.12.2 Color Look-up Table (LUT) The Color Look-up Table (LUT) is stored in an on-chip RAM that is separate from the OSD RAM. The LUT is 64 colors by 16-bit in a RGB 5:5:5 format (bit 0 selectively enables blending with scaler data.
4.13 General Purpose Inputs and Outputs (GPIO's)
The GMZAN3 has up to 11 general-purpose input/output (GPIO) pins for the GMZAN3L and five GPIO for the GMZAN3T.
4.14 Bootstrap Configuration Pins
The GMZAN3 has three bootstrap pins
Table 19.
Bootstrap Signals
Signal Name
2_WIRE_ADDR_SEL
Pin Name
HDATA[3]
Description
If using 2-wire protocol, this selects one of the two slave addresses 0 = 0x70 & 0x71 1 = 0x94 & 0x95 To select Host Interface Configuration 00 Muxed Address/Data (AD) 8051 8-bit parallel interface 01 Reserved 10 2-wire interface 11 6-wire Genesis interface TCLK Selection 0 External oscillator (input on TCLK pin) 1 Xtal and internal oscillator (In this mode, it is always recommended to use a 10K pull-up resistor)
HP[1:0]
HDATA/AD/HP[1:0]
OSC_SEL
HDATA2/AD2/OSC_SEL
4.15 Host Interface
GMZAN3 contains many internal registers that control its operation. These are described in the GMZAN3 Register Listing (C0523-DSL-01). Option 1: A direct 8051 muxed 8-bit address/data port supports high-speed access. Option2: A serial host interface is provided to allow an external device to peek and poke registers in the GMZAN3. This is done using a 2-wire serial protocol. Note that 2-wire host interface requires bootstrap settings as described in Table 19.
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4.15.1 Host Interface Command Format - for 2 or 6-wire Transactions on the 2-wire host protocol occurs in integer multiples of bytes (i.e. 8 bits or two nibbles respectively). These form an instruction byte, a device register address and/or one or more data bytes. This is described in Table 20.
The first byte of each transfer indicates the type of operation to be performed by the GMZAN3. The table below lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte will vary depending on the instruction chosen. By utilizing these modes effectively, registers can be quickly configured.
The two LSBs of the instruction code, denoted 'A9' and 'A8' in Table 20 below, are bits 9 and 8 of the internal register address respectively. Thus, they should be set to `00' to select a starting register address of less than 256, `01' to select an address in the range 256 to 511, and '10' to select an address in the range 512 to 767. These bits of the address increment in Address Increment transfers. The unused bits in the instruction byte, denoted by 'x', should be set to `1'.
Table 20. Operation Mode
Write Address Increment Write Address No Increment (for table loading) Read Address Increment Read Address No Increment (for table reading) Reserved
Instruction Byte Map
Description
Allows the user to write a single or multiple bytes to a specified starting address location. A Macro operation will cause the internal address pointer to increment after each byte transmission. Termination of the transfer will cause the address pointer to increment to the next address location. Allows the user to read multiple bytes from a specified starting address location. A Macro operation will cause the internal address pointer to increment after each read byte. Termination of the transfer will cause the address pointer to increment to the next address location.
Bit
765432 1 0 0 0 0 1 x x A9 A8 0 0 1 0 x x A9 A8 1 0 0 1 x x A9 A8 1 0 1 0 x x A9 A8 0 0 1 1 x x A9 A8 0 1 0 0 x x A9 A8 1 0 0 0 x x A9 A8 1 0 1 1 x x A9 A8 1 1 0 0 x x A9 A8 0 0 0 0 x x A9 A8 0 1 0 1 x x A9 A8 0 1 1 0 x x A9 A8 0 1 1 1 x x A9 A8 1 1 0 1 x x A9 A8 1 1 1 0 x x A9 A8 1 1 1 1 x x A9 A8
Spare
No operation will be performed
4.15.2 2-wire Serial Protocol The 2-wire protocol consists of a serial clock HCLK and bi-directional serial data line HFS. The bus master drives HCLK and either the master or slave can drive the HFS line (open drain) depending on whether a read or write operation is being performed. The GMZAN3 operates as a slave on the interface. The 2-wire protocol requires each device be addressable by a 7-bit slave address. The GMZAN3 is initialized on power-up to 2-wire mode by asserting bootstrap pins HP[1:0] to "10" and the slave address select bootstrap option HDATA3 on the rising edge of RESETn. By pulling HDATA3 high or low it is possible to select one of the two slave addresses: 0x94 & 0x95 (for HDATA=1) or 0x70 & 0x71 (for HDATA=0). This provides flexibility to configure the system consisting of multiple devices with the same slave address.
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A 2-wire data transfer consists of a stream of serially transmitted bytes formatted as shown in the figure below. A transfer is initiated (START) by a high-to-low transition on HFS while HCLK is held high. A transfer is terminated by a STOP (a low-to-high transition on HFS while HCLK is held high) or by a START (to begin another transfer). The HFS signal must be stable when HCLK is high, it may only change when HCLK is low (to avoid being misinterpreted as START or STOP).
HCLK HFS START
1 A6
2 A5
3 A4
4 A3
5 A2
6 A1
7 A0
8 R/W
9 ACK
1 D7
2 D6 DATA BYTE
8 D0
9 ACK STOP
ADDRESS BYTE Receiver acknowledges by holding SDA low
Figure 26.
2-Wire Protocol Data Transfer
Each transaction on the HFS is in integer multiples of 8 bits (i.e. bytes). The number of bytes that can be transmitted per transfer is unrestricted. Each byte is transmitted with the most significant bit (MSB) first. After the eight data bits, the master releases the HFS line and the receiver asserts the HFS line low to acknowledge receipt of the data. The master device generates the HCLK pulse during the acknowledge cycle. The addressed receiver is obliged to acknowledge each byte that has been received. The Write Address Increment and the Write Address No Increment operations allow one or multiple registers to be programmed with only sending one start address. In Write Address Increment, the address pointer is automatically incremented after each byte has been sent and written. The transmission data stream for this mode is illustrated in Figure 27 below. The highlighted sections of the waveform represent moments when the transmitting device must release the HFS line and wait for an acknowledgement from the GMZAN3 (the slave receiver).
HCLK
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
9
HFS START
DEVICE ADDRESS
R/W ACK
OPERATION CODE
A9 A8
ACK
REGISTER ADDRESS
ACK
DATA
DATA
ACK
Two MSBs of register address
STOP
Figure 27.
2-Wire Write Operations (0x1x and 0x2x)
The Read Address Increment (0x90) and Read Address No Increment (0xA0) operations are illustrated in Figure 28. The highlighted sections of the waveform represent moments when the transmitting device must release the HFS line and waits for an acknowledgement from the master receiver. Note that on the last byte read, no acknowledgement is issued to terminate the transfer.
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H LK C
HS F
D V EA D E S E IC D R S
R AK /W C
O E A IO C D PRT N OE
AK C
R G T RA D E S E IS E D R S
AK C
D V EA D E S E IC D R S
R AK /W C
DT AA
DT AA
AK C
DT AA
SR TA T
SR TA T
SO TP
Figure 28.
2-Wire Read Operation (0x9x and 0xAx)
Please note that in all the above operations the operation code includes two address bits, as described in Table 20. 4.15.3 8-bit Parallel Interface The 8-bit parallel interface connects to the external 8051 microcontroller's external memory interface utilizing the following signals: AD[7..0], ALE, WR#, RD#. An additional input signal (REG_MEM) is used to distinguish between the register set and the OSD SRAM. When REG_MEM is held low the GMZAN3 register set is selected and when it is held high the OSD SRAM will be active. The bus timing requirements are given in Table 27 and Table 28. The OSD SRAM is R/W accessed in "pages" of 256 bytes. The ALE signal is used to latch the 8-bits of address on the microprocessor's multiplexed Address/Data bus.
MCU AD[7..0] ALE RDn WRn Output Port AD[7..0]
ZAN3
ALE RDn WRn MEM_REG
Figure 29.
8-bit Parallel Interface
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GMZAN3 Preliminary Data Sheet
4.16 Miscellaneous Functions
4.16.1 Low Power State The GMZAN3 provides a low power state in which the clocks to selected parts of the chip may be disabled (see Table 22) and the ADC powered-off. 4.16.2 Pulse Width Modulation (PWM) Back Light Control Many of today's LCD back light inverters require both a PWM input and variable DC voltage to minimize flickering (due to the interference between panel timing and inverter's AC timing), and adjust brightness. Most LCD monitor manufactures currently use a microcontroller to provide these control signals. To minimize the burden on the external microcontroller, the GMZAN3 generates these signals directly. There are two pins available for controlling the LCD back light, PWM0/GPIO0 and PWM1/GPIO1. The duty cycle of these signals is programmable. They may be connected to an external RC integrator to generate a variable DC voltage for a LCD back light inverter or other applications. Panel HSYNC or TCLK may be used as the clock for the counter generating this output signal.
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GMZAN3 Preliminary Data Sheet
5 Electrical Specifications
The following targeted specifications have been derived by simulation.
5.1 Preliminary DC Characteristics
Table 21.
PARAMETER 3.3V Supply Voltages 1.8V Supply Voltages
(1,2) (1.2)
Absolute Maximum Ratings
SYMBOL VVDD_3.3 VVDD_1.8 VIN5Vtol VIN VESD ILA TA TSTG TJ
(3)
MIN -0.3 -0.3 -0.3 -0.3
TYP
MAX 3.6 1.98 5.5 3.6 2.0 100
UNITS V V V V kV mA C C C C/W C/W C C
Input Voltage (5V tolerant inputs) (1,2) Input Voltage (non 5V tolerant inputs) (1,2) Electrostatic Discharge Latch-up Ambient Operating Temperature Storage Temperature Operating Junction Temp. Thermal Resistance (Junction to Air) Natural Convection Thermal Resistance (Junction to Case) Convection Soldering Temperature (30 sec.) Vapor Phase Soldering (30 sec.)
NOTES: (1) (2) (3) (4) All voltages are measured with respect to GND.
(4)
0 -40 0
70 150 125 37.6 16.0 220 220
GMZAN3 GMZAN3
JA_ZAN3 JC_ZAN3 TSOL TVAP
Absolute maximum voltage ranges are for transient voltage excursions. Package thermal resistance is based on a two-layer PCB. Package JA is improved on a PCB with four or more layers. Based on the figures for the Operating Junction Temperature, JC and Power Consumption in Table 22, the typical case temperature is calculated as TC = TJ - P x JC.
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GMZAN3 Preliminary Data Sheet
Table 22.
PARAMETER
GMZAN3L DC Characteristics
MIN TYP MAX UNITS POWER
SYMBOL
Power Consumption @ 95 MHz ACLK (4) Power Consumption @ Low Power Mode 3.3V Supply Voltages (AVDD and RVDD) 1.8V Supply Voltages (VDD and CVDD) Supply Current @ Low Power Mode (1) Supply Current @ 95 MHz ACLK * 1.8V supply (2) * 3.3V supply
(3) (1)
PXGA PLP VVDD_3.3 VVDD_1.8 ILP IZAN3_XGA IZAN3_XGA IZAN3_XGA INPUTS 3.15 1.71 3.3 1.8
0.824 0.025 3.45 1.89 9
W W V V mA
187 138
mA mA
High Voltage Low Voltage Clock High Voltage Clock Low Voltage High Current (VIN = 5.0 V) Low Current (VIN = 0.8 V) Capacitance (VIN = 2.4 V)
VIH VIL VIHC VILC IIH IIL CIN OUTPUTS
2.0 GND 2.4 GND -25 -25
VDD 0.8 VDD 0.4 25 25 8
V V V V A A pF
High Voltage (IOH = 7 mA) Low Voltage (IOL = -7 mA) Tri-State Leakage Current
NOTES: (1) (2) (3) (4)
VOH VOL IOZ
2.4 GND -25
VDD 0.4 25
V V A
Low power mode or Suspend mode figures measured by shutting down all the blocks including the ADC. The CYSNC/SOG is the only block turned on to detect Sync signals. Includes pins CVDD_1.8, VDD_ADC_1.8 and VDD_RPLL_1.8. Includes pins RVDD_3.3, AVDD_RED_3.3, AVDD_GREEN_3.3, AVDD_BLUE_3.3, AVDD_ADC_3.3, AVDD_3.3, AVDD_RPLL_3.3, AVDD_OUT_LV_3.3 and AVDD_LV_3.3. XGA input at 85Hz with on/off pattern to XGA output operating at room temperature
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GMZAN3 Preliminary Data Sheet
Table 23.
PARAMETER
GMZAN3T DC Characteristics
MIN TYP MAX UNITS POWER
SYMBOL
Power Consumption @ 95 MHz ACLK (4) Power Consumption @ Low Power Mode 3.3V Supply Voltages (AVDD and RVDD) 1.8V Supply Voltages (VDD and CVDD) Supply Current @ Low Power Mode (1) Supply Current @ 95 MHz ACLK * 1.8V supply (2) * 3.3V supply
(3) (1)
PXGA PLP VVDD_3.3 VVDD_1.8 ILP IZAN3_XGA IZAN3_XGA IZAN3_XGA INPUTS 3.15 1.71 3.3 1.8
0.812 0.025 3.45 1.89 9
W W V V mA
178 149
mA mA
High Voltage Low Voltage Clock High Voltage Clock Low Voltage High Current (VIN = 5.0 V) Low Current (VIN = 0.8 V) Capacitance (VIN = 2.4 V)
VIH VIL VIHC VILC IIH IIL CIN OUTPUTS
2.0 GND 2.4 GND -25 -25
VDD 0.8 VDD 0.4 25 25 8
V V V V A A pF
High Voltage (IOH = 7 mA) Low Voltage (IOL = -7 mA) Tri-State Leakage Current
NOTES: (4) (5) (6) (4)
VOH VOL IOZ
2.4 GND -25
VDD 0.4 25
V V A
Low power mode or Suspend mode figures measured by shutting down all the blocks including the ADC. The CYSNC/SOG is the only block turned on to detect Sync signals. Includes pins CVDD_1.8, VDD_ADC_1.8 and VDD_RPLL_1.8. Includes pins RVDD_3.3, AVDD_RED_3.3, AVDD_GREEN_3.3, AVDD_BLUE_3.3, AVDD_ADC_3.3, AVDD_3.3, AVDD_RPLL_3.3, AVDD_OUT_LV_3.3 and AVDD_LV_3.3. XGA input at 85Hz with on/off pattern to XGA output operating at room temperature
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GMZAN3 Preliminary Data Sheet
5.2 Preliminary AC Characteristics
The following targeted specifications have been derived by simulation. All timing is measured to a 1.5V logic-switching threshold. The minimum and maximum operating conditions used were: TDIE = 0 to 125 C, Vdd = 1.71 to 1.89V, Process = best to worst, CL = 16pF for all outputs.
Table 24. Clock Domain
Main Input Clock (TCLK) ADC Clock (ACLK) HCLK Host Interface Clock (6-wire protocol) Reference Clock (RCLK) Display Clock (DCLK)
Maximum Speed of Operation
Max Speed of Operation
24MHz (14.3MHz recommended) 100MHz 5MHz 240MHz (220MHz recommended) 90MHz
Table 25.
Display Timing and DCLK Adjustments
Tap 0 (default) Min Max (ns) (ns) 1.0 4.5 1.0 4.5 0.5 4.5 1.0 4.5 Tap 1 Min Max (ns) (ns) 0.5 3.5 0.5 3.5 0.0 3.5 0.5 3.5 Tap 2 Min Max (ns) (ns) -0.5 2.5 -0.5 2.5 -1.0 2.5 -0.5 2.5 Tap 3 Min Max (ns) (ns) -1.5 1.5 -1.5 1.5 -2.0 1.5 -1.5 1.5
DP_TIMING ->
Propagation delay from DCLK to DA*/DB* Propagation delay from DCLK to DHS Propagation delay from DCLK to DVS Propagation delay from DCLK to DEN
Note: DCLK Clock Adjustments are the amount of additional delay that can be inserted in the DCLK path, in order to reduce the propagation delay between DCLK and its related signals.
Table 26.
Parameter SCL HIGH time SCL LOW time SDA to SCL Setup SDA from SCL Hold Propagation delay from SCL to SDA
2-Wire Host Interface Port Timing
Symbol TSHI TSLO TSDIS TSDIH TSDO3 MIN 1.25 1.25 30 20 10 TYP MAX Units us us ns ns ns
150
Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock)
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GMZAN3 Preliminary Data Sheet
Table 27.
Microcontroller Interface Timing (Muxed Address/Data) for Register Read/Write
Parameter Symbol Tasu Tah Tdw Tdh Tap Twp Trp Tra Trdly Trh Tacl MIN 10 5 5 5 10 4 30 10 15 2 30 TYP MAX Units ns ns ns ns ns Tref ns ns ns ns ns
AD valid to ALE trailing edge setup time Trailing edge of ALE to AD hold time WR# leading edge to AD valid delay Trailing edge of WR# to AD hold time ALE pulse width WR# pulse width RD# pulse width RD#/WR# trailing edge to ALE leading edge Leading edge of RD# to AD data delay Trailing edge of RD# to AD hold time Trailing edge of ALE to WR# or RD# (command) leading edge Note: Tref = HOST_CLK = TCLK or (RCLK/4)
5
T ap
A LE T asu AD T ah
ADDRESS
DATA
ADDRESS
T dh W R# T acl T dw T wp T ra
Figure 30.
Microcontroller Register Write Cycle
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GMZAN3 Preliminary Data Sheet
T ap
A LE T asu AD T ah
ADDRESS
DATA
ADDRESS
T rdly RD# T acl T rp T rh
T ra
Figure 31.
Microcontroller Register Read Cycle
Table 28.
Microcontroller Interface Timing (Muxed Address/Data) for OSD Memory Read/Write
Symbol Tasu Tah Tdw Tdh Tap Twp Trp Tra Trdly Trh Tacl MIN 10 5 5 5 10 4 30 4 10 2 30 TYP MAX Units ns ns ns ns ns Tref ns Tref Tref ns ns
Parameter AD valid to ALE trailing edge setup time Trailing edge of ALE to AD hold time WR# leading edge to AD valid delay Trailing edge of WR# to AD hold time ALE pulse width WR# pulse width RD# pulse width WR# trailing edge to ALE leading edge Trailing edge of ALE to AD data valid delay Trailing edge of RD# to AD hold time Trailing edge of ALE to WR# or RD# (command) leading edge Note: Tref = HOST_CLK = (RCLK/4)
5
T ap
A LE T asu AD T ah
ADDRESS
DATA
ADDRESS
T dh W R# T acl T dw T wp T ra
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GMZAN3 Preliminary Data Sheet
Figure 32.
Microcontroller OSD CCF Write Cycle
T ap
A LE T asu AD T ah
ADDRESS
DATA
ADDRESS
T rdly RD# T acl T rh T rp
Figure 33.
Microcontroller OSD CCF Read Cycle
6 Ordering Information
Order Code GMZAN3T GMZAN3L Application XGA with TTL Panel interface XGA with single LVDS transmitter Panel interface Package 128-pin PQFP 128-pin PQFP Temperature Range 0-70C 0-70C
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GMZAN3 Preliminary Data Sheet
7 Mechanical Specifications
NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H- . 2. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion can be 0.08mm total in excess of dimension b at maximum material condition. Dambar cannot be located on the lower radius or the lead foot.
Figure 34.
GMZAN3 128-pin PQFP Mechanical Drawing
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